The present invention relates to multi-address space control and more particularly to a multi-address space control method and system suitable for the transfer of data between different address spaces.
As the instructions for the data transfer between two virtual address spaces (herein called first space and second space) produced by different address translation tables, there are known, for example, MVCP (Move to Primary) and MVCS (Move to Secondary) instructions as disclosed in IBM System/370 Principles of Operation GA22-7000-8. An MVCS instruction will be explained in the following:
With an MVCS instruction, data in the first space is transferred to the second space. For accessing the first space, a storage protect check is executed using a program status word (PSW) key. For accessing the second space, a key-controlled protection check is executed using a second space access protection key (called hereinafter a second space key) in a general register (GR) designated by an instruction operand.
An MVCS instruction in conventional systems has been processed as in the following:
According to a first scheme in conventional systems, at the step of accessing the second space, address translation is conducted by changing the contents of an address translation table leading address (hereinafter called a segment table origin (STO)) register which contains the first address (leading address) of an address translation table.
After a real address for the second operand address of the first space is obtained, a real address for the first operand address of the second space is obtained using the above-described second space access step. Using the obtained real address, a data transfer from the first to the second space is performed.
However, if an operand address designates a plurality of pages, it is necessary that the operand address be translated into a real address for each page and that an access exception be checked for each page if it is detected or not. The access exception includes a translation designation exception, segment translation exception, page translation exception, addressing exception, key control protection exception, page protection exception, lower address protection exception and no implemented memory. Further, it is necessary to store a logical address for notifying of an access interruption when an access exception is detected or a program event is to be interrupted, thus resulting in complicated processing.
According to a second scheme in conventional systems, second operand data in the first space are sequentially read and temporarily stored in a hardware work area. The second space access step described in the above first scheme is executed and thereafter, the data in the work area are sequentially written in the second space. However, a work area having as large a space as the data length to be transferred is required. Further, the transfer operation of operand data is not executed through repetition of second-operand read operation and first-operand write operation so that the processing speed is lowered in some cases.
In both first and second schemes, a PSW key is changed to a second space key to access the second space for storage protection check. Further, if an interruption occurs during data transfer, it is necessary to immediately set the contents of the address translation table top address at an initial value. Particularly for processing an MVCP or MVCK instruction, when an interruption occurs in both schemes while a PSW key is changed to a second space key, it is necessary to immediately set the program status word at an initial value. Furthermore, it is necessary to change a program status word every time a different address space is accessed, thereby resulting in complicated processing and low processing speed.
Schemes of this type are disclosed, for example, in JP-A-57-8860, and U.S. Pat. No. 4,521,846 (JP-B-60-41379).